Fabrication of a semiconductor device and an integrated circuit thereof begins with a semiconductor substrate and employs film formation, ion implantation, photolithographic, etching and deposition techniques to form various structural features in or on the substrate to attain individual circuit components which are then interconnected to ultimately form an integrated semiconductor device. Escalating requirements for high densification and performance associated with ultra large-scale integration (ULSI) semiconductor devices requires smaller design features, increased transistor and circuit speeds, high reliability and increased manufacturing throughput for competitiveness. As the devices and features shrink, and as the drive for higher performing devices escalates, new problems are discovered that require new methods of fabrication or new arrangements or both.
There is a demand for large-scale and ultra large-scale integration devices employing high performance metal-oxide-semiconductor (MOS) devices. MOS devices typically comprise a pair of ion implanted source/drain regions in a semiconductor substrate and a channel region separating the source/drain regions. Above the channel region is a thin gate oxide and a conductive gate comprising conductive polysilicon or another conductive material. In a typical integrated circuit, a plurality of MOS devices of different conductivity types, such as n-type and p-type, and complementary MOS (CMOS) devices employing both p-channel and n-channel devices are formed on a common substrate. MOS technology offers advantages of significantly reduced power density and dissipation as well as reliability, circuit performance and cost advantages.
FIG. 1 illustrates a cross-sectional portion of an exemplary CMOS structure comprising a doped semiconductor substrate 10 typically of monocrystalline silicon of a first conductivity type (p or n). The CMOS structure further comprises field oxide area 12, gate oxide layer 14, conductive gate electrodes 16 and 18, typically of polysilicon, formed over gate oxide layer 14, and stepped source and drain regions 20 and 22 which include lightly or moderately doped shallow extensions 20A and 22A. Completing the MOS transistor precursor structure are insulative sidewall spacers 24A through 24D, formed on the side surfaces of each of gate electrodes 16 and 18.
The general steps in fabricating conventional MOS devices of different conductivity types on a single substrate are summarized in FIG. 2 with respect to the structure illustrated in FIG. 1. The process begins with a highly polished substrate of monocrystalline silicon where field oxide area 12 is formed, as by local oxidation of silicon (LOCOS) or shallow trench isolation (STI), in semiconductor substrate 10. Thin gate oxide 14 is thermally grown from about 25 .ANG. to about 50 .ANG. thick, and conductive gate electrodes 16 and 18 are formed from polysilicon at about 1200 .ANG. to about 2000 .ANG. thick. A photoresist mask is thereafter formed on the areas to be subsequently implanted, and substrate 10 is implanted, as by ion implantation, with n-type impurities to form lightly or moderately doped (NLDD) regions 20A, also called shallow source/drain extensions. The mask is then removed, and the areas previously implanted with impurities NLDD are masked with a second photoresist mask. Substrate 10 is thereafter implanted, as by ion implantation, with p-type impurities to form lightly or moderately doped (PLDD) regions 22A.
The second photoresist mask is then removed and sidewall spacers 24A through 24D are formed on the side surfaces of the gate electrodes 16 and 18, as by depositing a blanket layer of a dielectric material, such as silicon nitride, and anisotropically etching the dielectric material. A third photoresist mask is thereafter formed on the regions implanted with p-type impurities, and substrate 10 is implanted, as by ion implantation, with n-type impurities to form source/drain (NS/D) regions 20, which include lightly or moderately doped regions 20A. The third mask is then removed, and the areas previously implanted with impurities NS/D are masked with a fourth photoresist mask and substrate 10 is thereafter implanted, as by ion implantation, with p-type impurities to form source/drain (PS/D) regions 22, which include regions 22A. Upon removal of the final mask, the structure shown in FIG. 1 remains.
Source/drain implants NS/D, PS/D are typically implanted at a higher energy and dosage than lightly or moderately doped implants NLDD, PLDD, so source/drain implants NS/D, PS/D penetrate deeper into substrate 10 than lightly or moderately doped implants NLDD, PLDD. Additionally, sidewall spacers 24A through 24D prevent moderate or heavy source/drain implants NS/D, PS/D from penetrating substrate 10 adjacent to or under gate electrodes 16 and 18 to obtain the desired device performance characteristics. Thus, source/drain regions 20 and 22 have a step corresponding to spacers 24A through 24D. After the implantation process, the substrate is heated to diffuse and electrically activate the implants to form the heavily doped contact regions in the substrate. This annealing, drive-in process comprises heating the implanted substrate for a short period of time at a moderate temperature 900.degree. C. to about 1100.degree. C.
Additional process steps, such as the formation of metal contacts to electrically connect various features, formation of insulative layers to isolate the various features, and formation of inter-level metallization, complete and integrate the device.
The high temperatures needed during conventional source/drain formation precludes the use of materials, particularly gate electrode materials, that would melt, decompose, or otherwise adversely affect the process. Hence, conventional techniques for forming MOS devices involve a complex series of steps each of which precludes the use of certain materials.
Of particular importance in MOS devices is the composition and dimensional accuracy of the gate electrode structure, which includes the gate electrode and the underlying gate oxide. The gate electrode's thickness, length, composition, etc. are critical since the gate electrode controls the flow of electrons and is vital to proper device operation, particularly as the dimensions of device features are reduced into the sub-micron range. However, the gate electrode dimensions is limited by the resolution of the photolithographic process. Moreover, the choice of useful materials that can serve as a conductive gate electrode and underlying dielectric layer is limited to the those materials which can withstand the complex and extreme processing steps in the manufacture of MOS transistors, e.g. polysilicon and silicon dioxide, respectively.
Hence, it would be highly advantageous to develop a process which would permit the use of optimum materials in the formation of the gate electrode structure. It would also be highly advantageous to develop methodologies capable of optimum MOS transistor formation. Accordingly, there exists a need for a method of manufacturing MOS semiconductor devices with a reduced dimensional gate structure and/or optimum materials that improves device performance.